Semiconductor devices, such as, fin-type field effect transistors, typically include a large number of transistors within a single chip or wafer area. As the integration density of transistors continues to increase, the footprint area occupied by individual transistors continues to decrease. This ever-decreasing transistor size can result in challenges to the performance characteristics of the transistors. These challenges include, for instance, dual channel devices caused by the diffusion of germanium from a region designated for a p-type field effect transistor (PFET) device into a region designated for an n-type field effect transistor (NFET) device, during the fabrication of silicon fins in the NFET region and silicon germanium fins in a PFET region, respectively.
Accordingly, enhancements in fin device structures and fabrication methods continue to be desired for enhanced performance and commercial advantage.